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Freescale Semiconductor Technical Data
Document Number: MC33186 Rev. 6.0, 10/2006
H-Bridge Driver
The 33186 is a monolithic H-Bridge ideal for fractional horsepower DC-motor and bi-directional thrust solenoid control. The IC incorporates internal control logic, charge pump, gate drive, and low RDS(ON) MOSFET output circuitry. The 33186 is able to control continuous inductive DC load currents up to 5.0 A. Output loads can be pulse width modulated (PWM-ed) at frequencies up to 10 kHz. The 33186 is parametrically specified over a temperature range of -40C TA 125C, 5.0 V V+ 28 V. The IC can also be operated up to 40 V with de-rating of the specifications. The IC is available in a surface mount power package with exposed pad for heat sinking. Features * Overtemperature, Short-Circuit Protection, and Overvoltage Protection against Transients up to 40 V at VBAT Typical * RDSon = 150 m for each output Transistor at 25C * Continuous DC Load Current 5 A (TC < 100C) * Output Current Limitation at typ 6,5 A +/- 20% * Short-Circuit Shutdown for Output Currents over 8 A * Logic Inputs TTL/CMOS Compatible * Operating Frequency up to 20 kHz * Undervoltage Disable Function * Diagnostic Output, 2 Disable Input * Coding Input for Alternative Functions * Stable Operation with an External Capacitance of Maximum 47 F at VBAT * Pb-Free Packaging Designated by Suffix Code VW
DH SUFFIX VW SUFFIX (PB-FREE) PLASTIC PACKAGE 98ASH70702A 20-PIN HSOP
33186
H-BRIDGE MOTOR DRIVER
ORDERING INFORMATION
Device MC33186DH1/R2 - 40C to 125C MC33186VW1/R2 20 HSOP Temperature Range (TA) Package
5.0 V CP
33186
VBAT OUT1
VPWR
SF MCU or DSP IN1 IN2 DI1 DI2
MOTOR OUT2 PGND
Figure 1. 33186 Simplified Block Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products.
(c) Freescale Semiconductor, Inc., 2007. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
CP VBAT VBAT Internal 5V Charge-Pump
VBAT
SF
Undervoltage
Overcurrent High-Side IN1 IN2 Logic DI1 DI2
Overtemperature Gate Control: 3-4 Gate Control: 1-2
OUT1 OUT2 Overcurrent Current Limit Low-Side
COD
Current limitation
PGND
Figure 2. 33186 Simplified Internal Block Diagram
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Analog Integrated Circuit Device Data Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
PIN CONNECTIONS
AGND SF IN1 VBAT VBAT OUT1 OUT1
1 2 3 4 5 6 7 8 9
20 19 18 17 16 15 14 13 12 11
NC IN2 DI1 CP VBAT OUT2 OUT2 DI2 PGND PGND
COD PGND
PGND 10
Metal slug is connected to power ground
(Top View)
Figure 3. 33186 Pin Locations Table 1. 33186 Pin Description
Pin 9, 10, 11, 12 Metal slug 1 AGND Name PGND Description Power Ground. All the ground are connected together, they should be connected as short as possible on the PCB. Analog ground. All the ground are connected together, they should be connected as short as possible on the PCB. Open drain output, active low. Is set according to the truth table. When a fault appears, SF changes typically in less than 100 ms. Voltage controlled inputs with hysteresis
2
Output Status flag (SF)
3,13 18, 19 8
Inputs IN1, IN2, DI1, DI2, COD COD
When not connected or connected to GND, a stored failure will be reset by change of the voltagelevel on DI1 or DI2. When connected to VCC, the disable Pin DI1 and DI2 are inactive. A stored failure will be reset by change of the voltage-level on IN1 or IN2.
6, 7, 14, 15
OUT1, OUT2
H-Bridge outputs with integrated free-wheeling diodes.
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PIN CONNECTIONS
Table 1. 33186 Pin Description(continued)
Pin 4, 5, 16 Name VBAT Description The Pins 4 and 5 are internally connected. These Pins supply the left high side and the analog/logic part of the device. The Pin 16 supplies the right high side and the charge pump. The Pins 4, 5 and 16 should be connected together on the printed circuit board with connections as short as possible. Supervision and protection functions a) Supply voltage supervision The supply voltage is supervised. If it is below its specific threshold, the power stages are switched in tristate and the status flag is switched low. If the supply voltage is over the specific threshold again, the power stage switches independently into normal operation, according to the input Pins and the status flag is reset. b) Thermal supervision In case of overtemperature, the power stages are switched in tristate independent of the inputs signals and the status flag is switched low. If the level changes from high to low on DI1 (IN1) or low to high on DI2 (IN2), the output stage switches on again if the temperature is below the specified limit.The status-flag is reset to high level (Pin names in brackets refer to coding Pin = VCC). c) Supervision of overcurrent on high sides and low sides In case of over-current detection, the power stages are switched in tristate independent of the inputs signals and the status flag is set. If the level changes from high to low on DI1 (IN1) or low to high on DI2 (IN2) the output stage switches on again and the status flag is reset to high level (Pin names in brackets refer to coding Pin = VCC). The output stage switches into the mode defined by the inputs Pins provided, and/if the temperature is below the specified limits. d) Current limiting on low sides The maximum current which can flow under normal operating conditions is limited to Imax = 6,5 A +/- 20%. When the maximum current value is reached, the output stages are switched tristate for a fixed time. According to the time constant the current decreases until the next switch on occurs. See page 8 for schematics. 17 CP Charge Pump output Pin A filtering capacitor (up to 33 nF) can be connected between Pin 17 and Gnd. Device can operate without external capacitor, although Pin 17 decoupling capacitor help in noise reduction and allows the device to perform a maximum speed, timing and PWM frequency.
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings ELECTRICAL RATINGS Supply Voltage Static Destruction Proof Dynamic Destruction Proof t < 0,5 s Logic Inputs (IN1, IN2, DI1, DI2, CODE) Output Status - Flag SF THERMAL RATINGS Junction Temperature Storage Temperature Ambient Temperature Thermal Resistance (with power applied on 2 power MOS) Thermal Resistance (with power applied on 2 power MOS) Peak Package Reflow Temperature During Reflow (1), (2) TJ TS TA - 40 - 55 - 40 - - - +150 +125 +125 C C C VBAT VBat U USF - 1.0 - 2.0 - 0.5 - 0.5 - - - - 28 40 7.0 7.0 V V V Symbol Min Typ Max Unit
RthJC
-
-
+1.5
K/W
RthJC TPPRT
-
- Note 2.
+1.5
K/W C
Notes 1. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 2. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. STATIC ELECTRICAL CHARACTERISTICS Characteristic noted under conditions -40C to +125 C, VBAT from 5 V to 28 V, unless otherwise note. Typical values reflect approximate mean at 25C, nominal VCC, at time of device characterization.
Characteristics POWER SUPPLY Operating Range: Static Dynamic (t < 500 ms) Stand-by current f = 0 to 10 KHz; IOUT = 0 A VBAT-undervoltage switch-off (without load) Switch-off Voltage Switch-on Voltage Hysteresis CHARGE-PUMP SUPPLY VBAT = 4.15 V VBAT < 40 V LOGIC INPUTS Input High Input Low Input Hysteresis Input Pull Up Current (IN1, IN2, DI1) UIN = 0.0 V Input Pull Down Current (DI2,COD)(3) UDI2 = 5.0 V POWER OUTPUTS: OUT1, OUT2 Switch on resistance: ROUT - VBAT; ROUT - GND VBAT = 5 to 28 V; CCP = 0 to 33 nF Switch-off Current during Current Limitation on Low Sides Switch-off Time during Current Limitation on Low Sides Blanking Time during Current Limitation on Low Sides (IOUT) MAX tA tB - 5.2 15 12 - 6.5 20.5 16.5 300 7.8 26 21 m A s s IDI2 - 25 100 A VINH VINL U I 3.4 - 0.7 - 200 - - 1.0 - 80 - 1.4 - - V V V A VCP - VBAT VCP - VBAT 3.35 - - - - 20 V V 4.15 4.5 150 4.4 4.75 - 4.65 5.0 - V V mV I VBAT - - 35 mA VBAT VBAT 5.0 - - - 28 40 V V Symbol Min Typ Max Unit
Notes 3. In case of negative voltage at OUT2 (respectively OUT1) this maximum pull down current at DI2 (respectively COD) Pin can be exceeded. This happens during recirculation when the current is flowing in the low side. See curve 22.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. STATIC ELECTRICAL CHARACTERISTICS(continued) Characteristic noted under conditions -40C to +125 C, VBAT from 5 V to 28 V, unless otherwise note. Typical values reflect approximate mean at 25C, nominal VCC, at time of device characterization.
Characteristics High Side Overcurrent Detection Low Side Overcurrent Detection Leakage Current Output Stage Switched off Free-Wheeling Diode Forward Voltage IOU = 3.0 A Free-Wheeling Diode Reverse Recovery Time IFM =1.0 A, di/dt = 4.0 A/s Switch-off Temperature Hysteresis OUTPUT STATUS FLAG (OPEN DRAIN OUTPUT) Output High (SF not set) USF = 5.0 V Output Low (SF set) ISF = 300 A TIMING PWM frequency CCP = 33 nF Maximum Switching Frequency During Current Limitation VBAT = 6....28 V.....CCP = 33 nF Output ON Delay IN1.....>OUT1 or IN2.....>OUT2 Output OFF Delay IN1.....>OUT1 or IN2.....>OUT2 Output Switching Time CCP = 0 to 33 nF OUTiH.....OUTiL, OUTiL.....OUTiH, IOUT = 3.0 A Disable Delay Time DIi.....OUTi Turn off in Case of Overcurrent or Overtemperature Power On Delay Time (CCP = 33 nF)(5) tDDIS - - - - 4.0 1.0 8.0 8.0 5.0 s s ms tr, tf 2.0 - 5.0 s tDOFF - - 15 s tDON - - 15 s f - - 20 KHz f - - 10 KHz VSF - - 1.0 V ISF - - 10 A 160 20 - - 190 30 C C tRR - 2.0 5.0 s UD - - 2.0 V - - 100 A
(4)
Symbol IOCHS IOCLS
Min 11 8.0
Typ - -
Max - -
Unit A
Notes 4. In case of overcurrent, the time when the current is greater than 7.8 A is lower than 30 s, with a maximum frequency of 1 kHz. 5. This parameter corresponds to the time for CCP to reach its nominal value when VBAT is applied.
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ELECTRICAL CHARACTERISTICS TRUTH TABLE
TRUTH TABLE
Table 4. TRUTH TABLE
Device State DI1 (8) 1-Forward 2-Reverse 3-Free Wheeling Low 4-Free Wheeling High 5-Disable 1 6-Disable 2 7-IN1 Disconnected 8-IN2 Disconnected 9-DI1 Disconnected 10-DI2 Disconnected 11-Current Limit.active 12-Undervoltage(6) 13-Overtemperature(7) 14-Overcurrent(7) L L L L H X L L Z X L X X X Input Conditions DI2 (8) H H H H X L H H X Z H X X X IN1 H L L H X X Z X X X X X X X IN2 L H L H X X X Z X X X X X X Status SF(9) H H H H L L H H L L H L L L SF(10) H H H H H H H H H H H L L L OU1 H L L H Z Z H X Z Z Z Z Z Z Outputs OU2 L H L H Z Z X H Z Z Z Z Z Z
Notes 6. In case of undervoltage, tristate and status-flag are reset automatically. 7. Whenever overcurrent or overtemperature is detected, the fault is stored (i.e.status-flag remains low). The tristate conditions and the status-flag are reset via DI1 (IN1) or DI2 (IN2). Pin names in brackets refer to coding Pin (COD = VCC). 8. If COD = VCC then DI1 and DI2 are not active. 9. COD = nc or GND 10. COD = VCC
L = Low H = High X = High or Low Z = High impedance (all output stage transistors are switched off).
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ELECTRICAL CHARACTERISTICS
10k Ccp=33nF VBAT Voltage Regulator VBAT VCC 47F
Power Ground SF IN1 Micro controller CP
IN2 OUT1 DI1 OUT2 DI2 M
COD
GND
Power Ground
Figure 4. Typical Application
INn
50%
50%
tDON
tDOFF 90% 10%
OUn
Figure 5. Output Delay Time
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ELECTRICAL CHARACTERISTICS
DIn
50%
tDDIS
OUn
10%
Z
Figure 6. Disable Delay Time
90%
90%
OUn
10% tf
10% tr
Figure 7. Output Switching Time
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
Loadcurrent
> 8A TYP 6.5A
Overturned
A
Control signal
Status Flag
Detail A
tA 6.5A
Overcurrent detection tB
tA = switch-off time in current limitation tB = current limitation blanking time
Figure 8. Current Limitation on Low Side
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ELECTRICAL CHARACTERISTICS
13,5 13 12,5 IVBAT (mA) 12 11,5 11 10,5 10 9,5 9 -50 -25 0 25 50 75 T, TEMPERATURE (C) 100 125 VBAT=12V
2,83 2,82 2,81 2,80 VinH (V) 2,79 2,78 2,77 2,76 2,75 -50 -25 0 25 50 75 T, TEMPERATURE (C) 100 125
Figure 9. Stand-by Current vs. Temperature
Figure 12. High Threshold Input Voltage vs. Temperature
45 40 Tambient=25C without Ccp
5,00 4,90 4,80 4,70 VBAT(V) Switch on Voltage
35 30
Vcp (V)
100 125
4,60 4,50 4,40 4,30 4,20 -50 -25 0 25 50 75 T, TEMPERATURE (C) Switch off Voltage
25 20 15 10 5 0 0 5 10 15 20 25 BATTERY VOLTAGE (V) 30 35
Figure 10. VBAT Undervoltage vs. Temperature
1,89 1,88 1,87 1,86 VinL (V)
RDSon (m) 200 190 180 170 160 150 140 130 120 110 -50
Figure 13. Vcp vs. Battery Voltage
VBAT=5V without Ccp
1,85 1,84 1,83 1,82 1,81 -50 -25 0 25 50 75 T, TEMPERATURE (C) 100 125
-25
0
25
50
75
100
125
T, TEMPERATURE (C)
Figure 11. Low Threshold Input Voltage vs. Temperature
Figure 14. RDSON vs. Temperature
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
7,20 7,10 7,00 IOUT max (A) 6,90 6,80 6,70 6,60 6,50 6,40 6,30 -50 -25 0 25 50 75 100 125
ta=20.5s Imotor (1A/div)
Out1 (5V/div)
Out2 (5V/div)
T, TEMPERATURE (C)
Figure 15. Switch off Current vs. Temperature
17,50 17,00 16,50 IOCHS (A) 16,00 15,50 15,00 14,50 14,00 13,50 13,00 -50 -25 0 25 50 75 100 125 High side switch
Figure 18. Switch off Time
Out1 (5V/div)
tr=3.7s
T, TEMPERATURE (C)
Figure 16. Overcurrent Detection vs. Temperature
Figure 19. Output Switching Time: Tr
I(out) max= 7A
Out1 (5V/div)
Imotor (1A/div)
tf=2.6s
Figure 17. Current Limitation
Figure 20. Output Switching Time: Tf
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ELECTRICAL CHARACTERISTICS
in1 (1V/div)
I(5A/div)
Out1 (2V/div)
Iochs= 16A
tdoff=12.5s
Figure 21. Output OFF Delay
Figure 24. High Side Overcurrent High Side Detection
3.2 3 2.8 2.6 2.4 2.2 2
tdon=5.8s
Out1 (2V/div)
1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
in1 (1V/div)
I OUT2 (A)
Figure 22. Output ON Delay
Note: Current through internal recirculation diode, @125C in case of negative voltage at OUT2
di2 (1V/div)
Figure 25. Maximum Di2 Input Current vs. Iout2, current
Out1 (2V/div)
tdiss=0.9s
Figure 23. Disable Delay Time
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Analog Integrated Circuit Device Data Freescale Semiconductor
PACKAGING SOLDERING
PACKAGING
SOLDERING
The 20 HSOP package is designed for enhanced thermal performance. The particularity of this package is its copper base plate on which the power die is soldered. The base plate is soldered on a PCB to provide heat flow to the ambient and also to provide a large thermal capacitance. Of course, the more copper area on the PCB, the better the power dissipation and transient behavior. We characterized the 20 HSOP on a double side PCB. The bottom side area of the copper is 7.8 cm2. The top surface is 2.7 cm2, see Figure 26.
100
10
Rth (C/W) 1
0,1 0,001
0,01
0,1
1
10 t, Time (s)
100
1000
10000
Figure 27. PHSOP20 Thermal Response Figure 27 shows the thermal response with the device soldered on to the test PCB described on Figure 26.
Top Side
Bottom Side
Figure 26. PCB Test Layout
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PACKAGING PACKAGE DIMENSIONS
PACKAGE DIMENSIONS
Important: For the most current revision of the package, visit www.freescale.com and perform a keyword search on the 98A number listed below.
PIN ONE ID
h X 45 _ E2
1 20
E3
D
e/2
D1
10
11
B
EXPOSED HEATSINK AREA
E1
10X
E bbb Y A A2
M
A CB H
DATUM PLANE
E4 BOTTOM VIEW
NOTES: 1. CONTROLLING DIMENSION: MILLIMETER. 2. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.150 PER SIDE. DIMENSIONS D AND E1 DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 5. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE b DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE TIEBAR PROTRUSIONS. ALLOWABLE TIEBAR PROTRUSIONS ARE 0.150 PER SIDE. MILLIMETERS MIN MAX 3.000 3.400 0.100 0.300 2.900 3.100 0.00 0.100 15.800 16.000 11.700 12.600 0.900 1.100 13.950 14.450 10.900 11.100 2.500 2.700 6.400 7.200 2.700 2.900 0.840 1.100 0.350 BSC 0.400 0.520 0.400 0.482 0.230 0.320 0.230 0.280 1.270 BSC --- 1.100 q 0_ 8_ aaa 0.200 bbb 0.100 DIM A A1 A2 A3 D D1 D2 E E1 E2 E3 E4 L L1 b b1 c c1 e h
D2
18X
e
b1 c C
SEATING PLANE
GAUGE PLANE
SECTION W-W L1 W L (1.600) W
A1 A3
bbb C
q
DETAIL Y
DH1 SUFFIX VW1 SUFFIX (PB-FREE) CASE 979C-02 20-PIN HSOP ISSUE A PLASTIC PACKAGE 98ASH70702A ISSUE A
33186
16
EEE CCC EEE CCC
b aaa
M
c1
CA
DATE 07/22/98
Analog Integrated Circuit Device Data Freescale Semiconductor
ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 2.0)
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
Introduction This thermal addendum is provided as a supplement to the MC33186 technical datasheet. The addendum provides thermal performance information that may be critical in the design and development of system applications. All electrical, application, and packaging information is provided in the datasheet. Package and Thermal Considerations The MC33186 is offered in a 20 pin HSOP exposed pad, single die package. There is a single heat source (P), a single junction temperature (TJ), and thermal resistance (RJA). TJ
=
33186DW 33186VW
20-PIN HSOP-EP
RJA
.
P
The stated values are solely for a thermal performance comparison of one package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a package in an applicationspecific environment. Stated values were obtained by measurement and simulation according to the standards listed below.
DH SUFFIX VW SUFFIX (Pb-FREE) 98ASH70273A 20-PIN HSOP-EP Note For package dimensions, refer to the 33186 data sheet.
Standards
Table 5. Thermal Performance Comparison
Thermal Resistance RJA
(1), (2)
1.0 0.2 1.0
[C/W] 29 9.0
RJB (2), (3) RJA (1), (4) RJC (5)
0.2 69 2.0 * All measurements are in millimeters Soldermast openings 20 Pin HSOP-EP 1.6 mm Pitch 16.0 mm x 11.0 mm Body 12.3 mm x 7.1 mm Exposed Pad Thermal vias connected to top buried plane
Notes: 1. Per JEDEC JESD51-2 at natural convection, still air condition. 2. 2s2p thermal test board per JEDEC JESD51-5 and JESD51-7. 3. Per JEDEC JESD51-8, with the board temperature on the center trace near the center lead. 4. Single layer thermal test board per JEDEC JESD51-3 and JESD51-5. 5. Thermal resistance between the die junction and the exposed pad surface; cold plate attached to the package bottom side, remaining surfaces insulated.
Figure 28. Thermal Land Pattern for Direct Thermal Attachment According to JESD51-5
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ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 2.0)
A
AGND SF IN1 VBAT VBAT OUT1 OUT1 COD PGND PGND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 NC IN2 DI1 CP VBAT OUT2 OUT2 DI2 PGND PGND
33186DH1 Pin Connections
20-Pin HSOP-EP 1.6 mm Pitch 16.0 mm x 11.0 mm Body 12.3 x 7.1 mm exposed pad
Figure 29. Thermal Test Board
Device on Thermal Test Board Material: Single layer printed circuit board FR4, 1.6 mm thickness Cu traces, 0.07 mm thickness 80 mm x 100 mm board area, including edge connector for thermal testing Cu heat-spreading areas on board surface Natural convection, still air
Table 6. Thermal Resistance Performance
A [mm2] 0 300 600 RJA [C/W] 70 49 47
Outline:
Area A: Ambient Conditions:
RJA is the thermal resistance between die junction and ambient air.
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ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 2.0)
Thermal Resistance [C/W] Thermal Resistance [C/W]
80 80 70 70 60 60 50 50 40 40 30 30 20 20 10 10 0 0 0 0 300 300 Heat spreading area A [mm] Heat Spreading Area A [mm2] 600 600
x
RJA [C/W]
Figure 30. Device on Thermal Test Board RJA
100 100 Thermal Resistance [C/W]
Thermal Resistance [C/W]
10 10
1
x
RJA [C/W]
0.1 0.1 1.00E-03 1.00E-03 1.00E-02 1.00E-01 1.00E-02 1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04 Time [s] Time[s]
Figure 31. Transient Thermal Resistance RJA 1 W Step Response, Device on Thermal Test Board Area A = 600 (mm2)
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Analog Integrated Circuit Device Data Freescale Semiconductor
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REVISION HISTORY
REVISION HISTORY
REVISION 5.0 6.0
DATE 5/2006 10/2006
DESCRIPTION OF CHANGES * * * * Implemented Revision History page Added Lead Free (Pb-Free) Part Number MC33186VW1 Updated data sheet formal Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from MAXIMUM RATINGS on page 5. Added note with instructions to obtain this information from www.freescale.com.
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Analog Integrated Circuit Device Data Freescale Semiconductor
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MC33186 Rev. 6.0 10/2006

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